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[InstCombine][SSE] Reduce DIVSS/DIVSD to FDIV if only first element is required
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Sun, 24 Apr 2016 18:35:59 +0000 (18:35 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Sun, 24 Apr 2016 18:35:59 +0000 (18:35 +0000)
commit4b5462f1194ee3d6bf7862d0ad70159b5a27eced
tree83ee5f5c884ba21134203b7ed9f4f3d14e476b1dtree | snapshot
parentbfccefd5142626be523fd1a668566512553b0b59commit | diff
[InstCombine][SSE] Reduce DIVSS/DIVSD to FDIV if only first element is required

As discussed on D19318, if we only demand the first element of a DIVSS/DIVSD intrinsic, then reduce to a FDIV call. This matches the existing FADD/FSUB/FMUL patterns.

llvm-svn: 267359
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp diff | blob | history
llvm/test/Transforms/InstCombine/x86-sse.ll diff | blob | history
llvm/test/Transforms/InstCombine/x86-sse2.ll diff | blob | history
Domain: System / Toolchain;