[PowerPC][Future] Add pld and pstd to future CPU
authorVictor Huang <wei.huang@ibm.com>
Tue, 28 Jan 2020 14:22:53 +0000 (08:22 -0600)
committerVictor Huang <wei.huang@ibm.com>
Tue, 28 Jan 2020 14:23:29 +0000 (08:23 -0600)
commit4b414d9adef26d5e840eb9a81ab5f30dc54996af
tree1e521a7c61b914fa773db275e15955ac5532c0a4
parent78dc64989c2f5c075ca74af9dac0c1cb4a2b1f4b
[PowerPC][Future] Add pld and pstd to future CPU
Add the prefixed instructions pld and pstd to future CPU. These are load and
store instructions that require new operand types that are 34 bits. This patch
adds the two instructions as well as the operand types required.

Note that this patch also makes a minor change to tablegen to account for the
fact that some instructions are going to require shifts greater than 31 bits
for the new 34 bit instructions.

Differential Revision: https://reviews.llvm.org/D72574
16 files changed:
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/test/CodeGen/PowerPC/future-check-features.ll
llvm/test/MC/Disassembler/PowerPC/future-invalid.txt
llvm/test/MC/Disassembler/PowerPC/futureinsts.txt
llvm/test/MC/PowerPC/future-errors.s [new file with mode: 0644]
llvm/test/MC/PowerPC/future.s