[SVE][CodeGen] Relax all true isel requirement for predicated operations that have...
authorPaul Walker <paul.walker@arm.com>
Mon, 16 Jan 2023 01:37:50 +0000 (01:37 +0000)
committerPaul Walker <paul.walker@arm.com>
Sat, 4 Feb 2023 12:01:35 +0000 (12:01 +0000)
commit4b051b4248bb6f9971dd1cf87fe311ebe9be917e
tree14b2ff936f90b5970ae60813d5f1323336d79c94
parent5b2549b0d2834a653be60b52885bdc9f21abc2ee
[SVE][CodeGen] Relax all true isel requirement for predicated operations that have no side effects.

We have isel patterns to allow predicated operations to emit
unpredicated instructions when the predicate is all true. However,
the predicated operations named #_PRED have no requirement for the
result of the inactive lanes and so when those operations have no
side effects, floating point exceptions for example, we can also
safely emit unpredicated instructions. Doing this allows better
register allocation, instruction scheduling and also enables more
usage of instructions that take immediate operands.

NOTE: This patch does not convert all possible instances but
instead focuses on the cases that are testable once D141937 lands.

Depends on D141937

Differential Revision: https://reviews.llvm.org/D141938
23 files changed:
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-undef.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-shifts-undef.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
llvm/test/CodeGen/AArch64/sve2-sra.ll