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(parent: b0caac7) | patch
[X86][Haswell][SchedModel] Fix WriteMULm latency.
authorMichael Kuperstein <michael.m.kuperstein@intel.com>
Thu, 26 Feb 2015 14:30:09 +0000 (14:30 +0000)
committerMichael Kuperstein <michael.m.kuperstein@intel.com>
Thu, 26 Feb 2015 14:30:09 +0000 (14:30 +0000)
commit4af74496597ae02d67ecb6ef60bb8a59181ef1b5
tree073d1efebb60d490eba0ef9070d15f02c88f5622tree | snapshot
parentb0caac77dd81f3bbb863dbe91d489b36488f57cfcommit | diff
[X86][Haswell][SchedModel] Fix WriteMULm latency.

The latency for the WriteMULm class was set to 4, which is actually lower than the latency for WriteMULr (5).
A better estimate would be 4 added to WriteMULr, that is, 9.

llvm-svn: 230634
llvm/lib/Target/X86/X86SchedHaswell.td diff | blob | history
Domain: System / Toolchain;