phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initialization
authorPali Rohár <pali@kernel.org>
Fri, 24 Sep 2021 14:11:55 +0000 (16:11 +0200)
committerStefan Roese <sr@denx.de>
Fri, 8 Oct 2021 06:33:52 +0000 (08:33 +0200)
commit4adb16b29a31590f536b72e635370aff73732b4d
tree47fbda04a09ae3caa2763f0e17cb543de8cb096b
parent646a1522478a30889354a378b2617b4c08d2c9fb
phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initialization

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
Root Complex mode.

Same change was included in TF-A project:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
drivers/phy/marvell/comphy_a3700.c
drivers/phy/marvell/comphy_a3700.h