drm: bridge: icn6211: Add DSI lane count DT property parsing
authorMarek Vasut <marex@denx.de>
Thu, 7 Apr 2022 18:56:17 +0000 (20:56 +0200)
committerRobert Foss <robert.foss@linaro.org>
Tue, 19 Apr 2022 17:18:20 +0000 (19:18 +0200)
commit4ab85930b7183eaabdaffbcecd89c12e2aca071a
tree249afc616ed887c6111cde078c1dceaa590dce06
parent29d699a4c006940cf06f647ed02cc083234e8e33
drm: bridge: icn6211: Add DSI lane count DT property parsing

The driver currently hard-codes DSI lane count to two, however the chip
is capable of operating in 1..4 DSI lanes mode. Parse 'data-lanes' DT
property and program the result into DSI_CTRL register.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Maxime Ripard <maxime@cerno.tech>
Cc: Robert Foss <robert.foss@linaro.org>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
To: dri-devel@lists.freedesktop.org
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220407185617.179573-2-marex@denx.de
drivers/gpu/drm/bridge/chipone-icn6211.c