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(parent: 78c01a5) | patch
aarch64: Add vector implementations of exp routines
authorJoe Ramsay <Joe.Ramsay@arm.com>
Wed, 28 Jun 2023 11:19:39 +0000 (12:19 +0100)
committerSzabolcs Nagy <szabolcs.nagy@arm.com>
Fri, 30 Jun 2023 08:04:26 +0000 (09:04 +0100)
commit4a9392ffc27ad280f84779eea3ba01f2c134d1d8
tree8716efd89aadc70338eeff9622cfcbdd7ff7911etree | snapshot
parent78c01a5cbeb6717ffa2d4d66bb90ac5c39bd81a9commit | diff
aarch64: Add vector implementations of exp routines

Optimised implementations for single and double precision, Advanced
SIMD and SVE, copied from Arm Optimized Routines.

As previously, data tables are used via a barrier to prevent
overly aggressive constant inlining. Special-case handlers are
marked NOINLINE to avoid incurring the penalty of switching call
standards unnecessarily.

Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
15 files changed:
sysdeps/aarch64/fpu/Makefile diff | blob | history
sysdeps/aarch64/fpu/Versions diff | blob | history
sysdeps/aarch64/fpu/bits/math-vector.h diff | blob | history
sysdeps/aarch64/fpu/exp_advsimd.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/exp_sve.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/expf_advsimd.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/expf_sve.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c diff | blob | history
sysdeps/aarch64/fpu/test-double-sve-wrappers.c diff | blob | history
sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c diff | blob | history
sysdeps/aarch64/fpu/test-float-sve-wrappers.c diff | blob | history
sysdeps/aarch64/fpu/v_exp_data.c [new file with mode: 0644] blob
sysdeps/aarch64/fpu/vecmath_config.h diff | blob | history
sysdeps/aarch64/libm-test-ulps diff | blob | history
sysdeps/unix/sysv/linux/aarch64/libmvec.abilist diff | blob | history
Domain: System / Toolchain;