Don't cache the instruction and register info from the TargetMachine, because
authorBill Wendling <isanbard@gmail.com>
Fri, 7 Jun 2013 06:19:56 +0000 (06:19 +0000)
committerBill Wendling <isanbard@gmail.com>
Fri, 7 Jun 2013 06:19:56 +0000 (06:19 +0000)
commit4a7a408eaabed80418e9d60c76ef02aa9f7e6006
tree202a1760f8421c6c85972a205d486ed4a2844089
parent9e7261c87469548754ac83f98a53e985e820a381
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

llvm-svn: 183490
llvm/lib/Target/Hexagon/HexagonCallingConvLower.cpp
llvm/lib/Target/Hexagon/HexagonCallingConvLower.h
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.h
llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
llvm/lib/Target/Hexagon/HexagonMachineScheduler.h
llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
llvm/lib/Target/Hexagon/HexagonRegisterInfo.h