drm/i915/skl: don't toggle PW1 and MISC power wells on-demand
authorImre Deak <imre.deak@intel.com>
Wed, 4 Nov 2015 17:24:15 +0000 (19:24 +0200)
committerImre Deak <imre.deak@intel.com>
Tue, 17 Nov 2015 18:55:15 +0000 (20:55 +0200)
commit4a76f295bc01f8342d4d2591da0a95dafa227191
tree45d5b332285b610a1fbd1d39cfa95c5dfb0bfd41
parent73dfc227ff5c8e005120daefc19b8521b1adc203
drm/i915/skl: don't toggle PW1 and MISC power wells on-demand

With the DMC firmware installed we don't need to handle HW resources
that are handled automatically by the firmware. Besides being redundant
this can also interfere with the firmware, possibly getting it into a
broken/blocked state. The on-demand handling of PW1 was already half-way
removed, MISC IO was still handled in this way. After the last patch we
init/uninit these HW resources manually as part of the display core
init/uninit sequence, so we can now remove the on-demand handling for
these completely.

We still keep around the power wells (with no domains attached to them)
since the manual toggling during display core init/uninit happens via
the current API.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
[s/beeing/being/ in commit message (imre)]
Link: http://patchwork.freedesktop.org/patch/msgid/1446657859-9598-7-git-send-email-imre.deak@intel.com
drivers/gpu/drm/i915/intel_runtime_pm.c