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(parent: 1c50da4) | patch
clk: meson: fractional pll support
authorMichael Turquette <mturquette@baylibre.com>
Tue, 7 Jun 2016 01:08:15 +0000 (18:08 -0700)
committerMichael Turquette <mturquette@baylibre.com>
Thu, 23 Jun 2016 01:05:47 +0000 (18:05 -0700)
commit4a47295144ddbcf802fcddb3d7c0736d9a1f2e40
treee988e9fddbcae63d64496b086d9be5c81e2bbc21tree | snapshot
parent1c50da4f27cbfb588b59684b55eb7a087bb26ed1commit | diff
clk: meson: fractional pll support

Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add
in a couple of new bitfields for further dividing the clock rate to
achieve rates with fractional hertz.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
drivers/clk/meson/clk-pll.c diff | blob | history
drivers/clk/meson/clkc.h diff | blob | history
Domain: System / Kernel;