[MC][AArch64] Enable '+v8a' when nothing specified for MCSubtargetInfo
authorCHIANG, YU-HSUN (Tommy Chiang, oToToT) <ty1208chiang@gmail.com>
Fri, 22 Apr 2022 01:54:15 +0000 (09:54 +0800)
committerCHIANG, YU-HSUN (Tommy Chiang, oToToT) <ty1208chiang@gmail.com>
Thu, 28 Apr 2022 20:53:22 +0000 (04:53 +0800)
commit4a31af88a26726f4662a2923618fe45977d09356
treecfff544c9246e59c8c1fb12fc49aefe50bf4e178
parent61d54259ed2bb7e67c19f658153362d117f7079e
[MC][AArch64] Enable '+v8a' when nothing specified for MCSubtargetInfo

Since D110065, the 'R' profile support is added to LLVM. It turns the
`generic` cpu into the intersection of v8-a and v8-r. However, this
makes some backward compatibility problems. The original patch makes
the clang driver implicitly pass -march=armv8-a when only the triple
is specified. Since it only applies to clang, other tools like
llvm-objdump still faces the backward compatibility problem.

This patch applies the same idea to MC related tools by enabling '+v8a'
feature when nothing is specified (both CPU and FS are empty) for
MCSubtargetInfo creation.

This patch should fix PR53956.

Reviewed by: labrinea

Differential Revision: https://reviews.llvm.org/D124319
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
llvm/test/MC/AArch64/arm64-branch-encoding.s
llvm/test/MC/AArch64/arm64-system-encoding.s
llvm/test/MC/AArch64/basic-a64-instructions.s
llvm/test/MC/Disassembler/AArch64/arm64-branch.txt
llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt