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(parent: b329e07) | patch
GlobalISel/TableGen: Handle REG_SEQUENCE patterns
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 10 Sep 2019 17:57:33 +0000 (17:57 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 10 Sep 2019 17:57:33 +0000 (17:57 +0000)
commit4a23ae5e78798662c07c94cc708fd70fd5ae88f9
tree150d0da2d364da7052dd6d935ceed64d1b66dae4tree | snapshot
parentb329e0728b3eda7a1c754931e5c174b2b7ae51b3commit | diff
GlobalISel/TableGen: Handle REG_SEQUENCE patterns

The scalar f64 patterns don't work yet because they fail on multiple
results from the unused implicit def of scc in the result bit
operation.

llvm-svn: 371542
llvm/lib/Target/AMDGPU/SIInstructions.td diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir diff | blob | history
llvm/test/TableGen/GlobalISelEmitterRegSequence.td [new file with mode: 0644] blob
llvm/utils/TableGen/GlobalISelEmitter.cpp diff | blob | history
Domain: System / Toolchain;