[SVE] Code generation for fixed length vector loads & stores.
authorPaul Walker <paul.walker@arm.com>
Mon, 18 May 2020 18:12:38 +0000 (19:12 +0100)
committerPaul Walker <paul.walker@arm.com>
Tue, 23 Jun 2020 09:39:03 +0000 (09:39 +0000)
commit499c63288f4e3385e8d7311b214fb4f743e33234
tree578ad250cc9740041ed8e1068782407b45e0d748
parentb9c26a9cfe53da7ef96e13ef1aa7fe793b1b5d28
[SVE] Code generation for fixed length vector loads & stores.

Summary:
This patch adds base support for code generating fixed length
vector operations targeting a known SVE vector length. To achieve
this we lower fixed length vector operations to equivalent scalable
vector operations, whereby SVE predication is used to limit the
elements processed to those present within the fixed length vector.

Specifically this patch implements load and store operations, which
get lowered to their masked counterparts thusly:

  V = load(Addr) =>
    V = extract_fixed_vector(masked_load(make_pred(V.NumElts), Addr))

  store(V, (Addr)) =>
    masked_store(insert_fixed_vector(V), make_pred(V.NumElts), Addr))

Reviewers: rengolin, efriedma

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80385
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll [new file with mode: 0644]
llvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll [new file with mode: 0644]