review.tizen.org Git - platform/upstream/dotnet/runtime.git/commit

projects / platform / upstream / dotnet / runtime.git / commit

author	Egor Chesakov <Egor.Chesakov@microsoft.com>
	Mon, 10 Aug 2020 18:10:53 +0000 (11:10 -0700)
committer	GitHub <noreply@github.com>
	Mon, 10 Aug 2020 18:10:53 +0000 (11:10 -0700)
commit	4988c25c0be065da30981dcebec18da195c580af
tree	386c3266cc40aabc05462bb5092cbc1bf88e20cd	tree \| snapshot
parent	c2711f5ad327c82b66df170d6d2bf7835e8e6774	commit \| diff

Fix #33948 by decreasing number of tests per group (#40491)

70 files changed:

src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_Part0_r.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_Part0_ro.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_Part1_r.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_Part1_ro.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_Part2_r.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_Part2_ro.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_Part3_r.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_Part3_ro.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_Part4_r.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_Part4_ro.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_Part5_r.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_Part5_ro.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/Program.AdvSimd.Arm64_Part0.cs		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/Program.AdvSimd.Arm64_Part1.cs		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/Program.AdvSimd.Arm64_Part2.cs		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/Program.AdvSimd.Arm64_Part3.cs	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/Program.AdvSimd.Arm64_Part4.cs	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/Program.AdvSimd.Arm64_Part5.cs	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part0_r.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part0_ro.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part10_r.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part10_ro.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part11_r.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part11_ro.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part12_r.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part12_ro.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part13_r.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part13_ro.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part14_r.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part14_ro.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part15_r.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part15_ro.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part16_r.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part16_ro.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part1_r.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part1_ro.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part2_r.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part2_ro.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part3_r.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part3_ro.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part4_r.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part4_ro.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part5_r.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part5_ro.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part6_r.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part6_ro.csproj		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part7_r.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part7_ro.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part8_r.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part8_ro.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part9_r.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part9_ro.csproj	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part0.cs		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part1.cs		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part10.cs	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part11.cs	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part12.cs	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part13.cs	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part14.cs	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part15.cs	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part16.cs	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part2.cs		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part3.cs		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part4.cs		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part5.cs		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part6.cs		diff \| blob \| history
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part7.cs	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part8.cs	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd_Part9.cs	[new file with mode: 0644]	blob
src/tests/JIT/HardwareIntrinsics/Arm/Shared/GenerateTests.csx		diff \| blob \| history

Domain: Dotnet / Core;

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