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(parent: 7550f59) | patch
radv: re-order IO slot layout for stages that aren't linked
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Mon, 28 Aug 2023 13:10:28 +0000 (15:10 +0200)
committerMarge Bot <emma+marge@anholt.net>
Wed, 30 Aug 2023 08:59:06 +0000 (08:59 +0000)
commit496a17bffeacd8172e9a3306ddcf4b919f196b79
tree262f57a0aa8f89ae3bf67fc46cf8543fbbb33996tree | snapshot
parent7550f59178e7cd4ec520830db0ce75d7bfb300b2commit | diff
radv: re-order IO slot layout for stages that aren't linked

Otherwise, if eg. PSIZ is exported the ESGS stride is wrong. This isn't
optimal yet but let's start with this to support separate compilation
of VS/TCS/TES/GS correctly first.

This fixes a bunch of issues when forcing separate compilation on RDNA2.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24908>
src/amd/vulkan/nir/radv_nir_lower_io.c diff | blob | history
Domain: Graphics System / GL;