i965: Use 8x4 aligned rectangles for HiZ operations on Broadwell.
authorKenneth Graunke <kenneth@whitecape.org>
Fri, 13 Jun 2014 22:26:40 +0000 (15:26 -0700)
committerKenneth Graunke <kenneth@whitecape.org>
Tue, 17 Jun 2014 00:23:21 +0000 (17:23 -0700)
commit49659ad90c501ae584b7d76ca98f35a8f57d40fe
tree0426a1f418006b1a194170f98622c89cf85cd723
parentfa35b272a04f1c0c598f1ba67f6e27fac96efa01
i965: Use 8x4 aligned rectangles for HiZ operations on Broadwell.

Like on Haswell, we need to use 8x4 aligned rectangle primitives for
hierarchical depth buffer resolves and depth clears.  See the comments
in brw_blorp.cpp's brw_hiz_op_params() constructor.  (The Broadwell
documentation confirms that this is still necessary.)

This patch makes the Broadwell code follow the same behavior as Chad and
Jordan's Gen7 BLORP code.  Based on a patch by Topi Pohjolainen.

This fixes es3conform's framebuffer_blit_functionality_scissor_blit
test, with no Piglit regressions.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
src/mesa/drivers/dri/i965/gen8_depth_state.c