[AArch64] Lower fcvtl2 (fpext) via tablegen patterns.
authorDavid Green <david.green@arm.com>
Sun, 23 Jul 2023 18:17:11 +0000 (19:17 +0100)
committerDavid Green <david.green@arm.com>
Sun, 23 Jul 2023 18:17:11 +0000 (19:17 +0100)
commit495bdfc7bb729ba22cf2b51d749f7789b0c2d9af
tree21d4e75512aecce330097a006e6a302f62d27c29
parent490bf27e53445fc4514c85142dec33ddf5bdcfe2
[AArch64] Lower fcvtl2 (fpext) via tablegen patterns.

This patch does two things. First it removes the tryHighFPExt DAG2DAG method
used to select fcvtl2 instructions, using tablegen patterns through
SelectExtractHigh instead. This essentially undoes D71515, in a way that should
hopefully avoid any regressions. The second is that a GI equivalent of
SelectExtractHigh is added in selectExtractHigh, from G_UNMERGE_VALUES. The
end result is that GlobalISel (and some constrained fpext) can now make use of
the fcvtl2 instructions, saving an extra dup/ext.

Differential Revision: https://reviews.llvm.org/D155871
llvm/include/llvm/Target/GlobalISel/Target.td
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
llvm/test/CodeGen/AArch64/fpext.ll