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(parent: 6f2e781) | patch
[RISCV] Generate march string from target features
authorwangpc <pc.wang@linux.alibaba.com>
Mon, 16 Jan 2023 03:07:34 +0000 (11:07 +0800)
committerwangpc <pc.wang@linux.alibaba.com>
Mon, 16 Jan 2023 04:03:59 +0000 (12:03 +0800)
commit4954c3c7b690c3cb484f6d18d3f3927aa65e21f4
tree53d7150957fc8b03642a802384123e942c308d9atree | snapshot
parent6f2e78195f644f024df5b5167e26bdd56b4c1c2bcommit | diff
[RISCV] Generate march string from target features

As what has been mentioned in D137517, this patch is to simplify
processors definitions in RISCV.td. We don't have to specify march
string since we can generate it from target features.

Reviewed By: fpetrogalli, kito-cheng

Differential Revision: https://reviews.llvm.org/D141479
llvm/lib/Target/RISCV/RISCV.td diff | blob | history
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp diff | blob | history
Domain: System / Toolchain;