[AArch64] Mark all instructions that read/write FPCR as doing so
authorJohn Brawn <john.brawn@arm.com>
Fri, 5 Nov 2021 10:11:00 +0000 (10:11 +0000)
committerJohn Brawn <john.brawn@arm.com>
Wed, 16 Nov 2022 12:29:50 +0000 (12:29 +0000)
commit49510c50200cf58c9f2dedf4e4ab36a16503878e
tree038bd8849bb509d1ea015b30c2067772a141d59a
parent4898568caa9f8f1e4d10ec415b46966a8dc19bd9
[AArch64] Mark all instructions that read/write FPCR as doing so

All instructions that can raise fp exceptions also read FPCR, with the
only other instructions that interact with it being the MSR/MRS to
write/read FPCR.

Introducing an FPCR register also requires adjusting
invalidateWindowsRegisterPairing in AArch64FrameLowering.cpp to use
the encoded value of registers instead of their enum value, as the
enum value is based on the alphabetical order of register names and
now FPCR is placed between FP and LR.

This change unfortunately means a large number of mir tests need to
be adjusted due to instructions now requiring an implicit fpcr operand
to be present.

Differential Revision: https://reviews.llvm.org/D121929
28 files changed:
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir
llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-dead-cc-defs-in-fcmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir
llvm/test/CodeGen/AArch64/machine-combiner-instr-fmf.mir
llvm/test/CodeGen/AArch64/machine-combiner-reassociate.mir
llvm/test/CodeGen/AArch64/machine-combiner.mir
llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
llvm/test/CodeGen/AArch64/strict-fp-opt.ll
llvm/test/CodeGen/AArch64/taildup-inst-dup-loc.mir
llvm/test/CodeGen/AArch64/wineh-frame1.mir
llvm/test/CodeGen/AArch64/wineh-frame2.mir
llvm/test/CodeGen/AArch64/wineh-frame4.mir
llvm/test/CodeGen/AArch64/wineh2.mir
llvm/test/CodeGen/AArch64/wineh3.mir
llvm/test/CodeGen/AArch64/wineh4.mir
llvm/test/CodeGen/AArch64/wineh8.mir
llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
llvm/test/DebugInfo/COFF/AArch64/codeview-b-register.mir
llvm/test/DebugInfo/COFF/AArch64/codeview-h-register.mir