projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 67f1f6f) | patch
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.store.format
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 19 Sep 2019 02:35:08 +0000 (02:35 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 19 Sep 2019 02:35:08 +0000 (02:35 +0000)
commit494243597b46350a248ee25efb0e3a728fc5900c
tree97557fb508cf639ac942c84816c9a0bed4f02dd0tree | snapshot
parent67f1f6ff8c07b5eef7239679a6b534efe933ceaacommit | diff
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.store.format

This needs special handling due to some subtargets that have a
nonstandard register layout for f16 vectors

Also reject some illegal types on other targets.

llvm-svn: 372293
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll [new file with mode: 0644] blob
Domain: System / Toolchain;