drm/i915: Fix the VDSC_PW2 power domain enum value
authorImre Deak <imre.deak@intel.com>
Tue, 22 Feb 2022 16:51:30 +0000 (18:51 +0200)
committerImre Deak <imre.deak@intel.com>
Mon, 28 Feb 2022 15:03:32 +0000 (17:03 +0200)
commit492c1ae2f27c327ef8d0f2019cac66408a41d808
tree884d0a945441044b77123d00f73eac062de10c1b
parent5c190e5394cc7773feaff1b54701a2c2f73ef011
drm/i915: Fix the VDSC_PW2 power domain enum value

The POWER_DOMAIN_TRANSCODER() macro depends on the
POWER_DOMAIN_TRANSCODER_A/B .. DSI_A/C enum values to be consecutive,
move POWER_DOMAIN_TRANSCODER_VDSC_PW2 after these to ensure this. The
wrong order didn't cause a problem, since the DSI_A/C domains are in
always-on power wells on all relevant platforms. The same power well
ends up being enabled/disabled when the VDSC_PW2 domain is selected
incorrectly.

While at it add a code comment about enum values that need to stay
consecutive.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220222165137.1004194-2-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_display_power.c
drivers/gpu/drm/i915/display/intel_display_power.h