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(parent: 2ab2483) | patch
dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
authorEmil Renner Berthing <kernel@esmil.dk>
Mon, 11 Jul 2022 18:59:24 +0000 (20:59 +0200)
committerJaehoon Chung <jh80.chung@samsung.com>
Mon, 24 Jul 2023 23:24:31 +0000 (08:24 +0900)
commit4910197a93183b04b6e7041ea343fafeffa544ab
treeabf8ce0e0b698a292eacda891f4d651743ff2c77tree | snapshot
parent2ab24830fceca14d0d2f6718d57401e533fd5142commit | diff
dt-bindings: clock: Add StarFive JH7110 system clock and reset generator

Add bindings for the system clock and reset generator (SYSCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml [new file with mode: 0644] blob
MAINTAINERS diff | blob | history
include/dt-bindings/clock/starfive,jh7110-crg.h [new file with mode: 0644] blob
include/dt-bindings/reset/starfive,jh7110-crg.h [new file with mode: 0644] blob
Domain: System / Kernel;