clk: meson: axg: fix the od shift of the sys_pll
authorYixun Lan <yixun.lan@amlogic.com>
Fri, 19 Jan 2018 01:47:01 +0000 (09:47 +0800)
committerYixun Lan <yixun.lan@amlogic.com>
Mon, 26 Mar 2018 02:13:27 +0000 (10:13 +0800)
commit48fe27347d9c43e7a1d3af2ca3c9be8c18cd35c2
tree48540b9d826c09af18b7d8b74e5c15fb71408afe
parentee8657ab98d614eb71191caf4560b690899610ea
clk: meson: axg: fix the od shift of the sys_pll

PD#159137: clk: meson: axg: fix the od shift of the sys_pll

According to datasheet, the od shift of sys_pll is 16,
fix the typo which introduced at previous commit.

Change-Id: I8d7e36b1178c0ab7f89791964fe4bb216c551d6d
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
drivers/amlogic/clk/axg/axg.c