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(parent: 1d42460) | patch
clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
authorChen-Yu Tsai <wens@csie.org>
Sun, 23 Jul 2017 10:27:44 +0000 (18:27 +0800)
committerChen-Yu Tsai <wens@csie.org>
Fri, 4 Aug 2017 04:05:20 +0000 (12:05 +0800)
commit48d5eb619c15847aba6757deb5c2c8badca2aece
tree1ee0062ccdb17d96195707cd3fbe1761269068b8tree | snapshot
parent1d42460a49347af4d1db345197e5d1277336b312commit | diff
clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change

This patch utilizes the new PLL clk notifier to gate then ungate the
PLL CPU clock after rate changes. This should prevent any system hangs
resulting from cpufreq changes to the clk.

Reported-by: Ondrej Jirman <megous@megous.com>
Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/sunxi-ng/ccu-sun8i-h3.c diff | blob | history
Domain: System / Kernel;