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(parent: e48668a) | patch
staging: iio: meter: ade7854: Fix alignment for DMA safety
authorJonathan Cameron <Jonathan.Cameron@huawei.com>
Sun, 7 Aug 2022 15:12:17 +0000 (16:12 +0100)
committerJonathan Cameron <Jonathan.Cameron@huawei.com>
Mon, 15 Aug 2022 21:30:01 +0000 (22:30 +0100)
commit48a1319164d9339ad50a25085cad6b879fef9fbe
tree84589864d17e7a607ce8e0938bd62205918e6d7atree | snapshot
parente48668a38bf420c660b07851985e6922fcf4b194commit | diff
staging: iio: meter: ade7854: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
Link: https://lore.kernel.org/r/20220807151218.656881-4-jic23@kernel.org
drivers/staging/iio/meter/ade7854.h diff | blob | history
Domain: System / Kernel;