[llvm][CodeGen] Fix issue for SVE gather prefetch.
authorFrancesco Petrogalli <francesco.petrogalli@arm.com>
Fri, 17 Apr 2020 18:05:31 +0000 (19:05 +0100)
committerFrancesco Petrogalli <francesco.petrogalli@arm.com>
Fri, 17 Apr 2020 18:23:28 +0000 (19:23 +0100)
commit48879c02bfc40017ec7d4dcfbd920ef949b53cf6
tree397e25feba34fcbea4cc4e5650d9809dc4d73191
parent681466f5e6412350a0b066791450e72325c2c074
[llvm][CodeGen] Fix issue for SVE gather prefetch.

Summary:
This change is fixing an issue where the dagcombine incorrectly used an addressing mode with scaled offsets (indices), instead of unscaled offsets.
Those addressing modes do not exist for `prfh` , `prfw` and `prfd`, hence we can reuse `prfb` because that has unscaled offsets, and because the pseudo-code in the XML spec suggests that the element size is not used for the amount of data that is prefetched by the instruction.

FWIW, GCC also emits a `prfb` for these cases.

Reviewers: sdesmalen, andwar, rengolin

Reviewed By: sdesmalen

Subscribers: tschuett, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78069
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-vect-base-invalid-imm-offset.ll