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drm/amdgpu/swsmu/smu12: fix force clock handling for mclk
authorAlex Deucher <alexander.deucher@amd.com>
Mon, 28 Sep 2020 18:16:25 +0000 (14:16 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 29 Sep 2020 20:14:03 +0000 (16:14 -0400)
commit485d531c695b0f5c87180a7724b85322d3967d39
treecc6e5b7b7d87d00e694278c5589b9933ec11e758tree | snapshot
parent808ec542c0297ae0b945ed0e6aba6f625ea2353ccommit | diff
drm/amdgpu/swsmu/smu12: fix force clock handling for mclk

The state array is in the reverse order compared to other asics
(high to low rather than low to high).

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1313
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c diff | blob | history
Domain: System / Kernel;