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[llvm][MIRVRegNamerUtils] Adding hashing on FrameIndex MachineOperands.
authorPuyan Lotfi <puyan@puyan.org>
Mon, 13 Jan 2020 18:30:20 +0000 (13:30 -0500)
committerPuyan Lotfi <puyan@puyan.org>
Mon, 13 Jan 2020 18:39:54 +0000 (13:39 -0500)
commit484a7472f1aa6906f2b66dc33bcf69cc8d5b9f29
tree9df15a6c2b089c3924991462fa9c93633fd6b982tree | snapshot
parent7aed43b60739653b13b8503f9df4c958c44feed8commit | diff
[llvm][MIRVRegNamerUtils] Adding hashing on FrameIndex MachineOperands.

This patch makes it so that cases where multiple instructions that differ only
in their FrameIndex MachineOperand values no longer collide. For instance:

%1:_(p0) = G_FRAME_INDEX %stack.0
%2:_(p0) = G_FRAME_INDEX %stack.1

Prior to this patch these instructions would collide together.

Differential Revision: https://reviews.llvm.org/D71583
llvm/lib/CodeGen/MIRVRegNamerUtils.cpp diff | blob | history
llvm/test/CodeGen/MIR/X86/mir-namer-hash-frameindex.mir [new file with mode: 0644] blob
Domain: System / Toolchain;