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(parent: 0580901) | patch
[RISCV] Make sure we always call tryShrinkShlLogicImm for ISD:AND during isel.
authorCraig Topper <craig.topper@sifive.com>
Sat, 22 Oct 2022 21:25:17 +0000 (14:25 -0700)
committerCraig Topper <craig.topper@sifive.com>
Sat, 22 Oct 2022 21:30:13 +0000 (14:30 -0700)
commit4830fa18aac6950d479a413c995c38fff56ac42c
tree2eab6de820bbe7c277d6f9beee25b06f48c003aetree | snapshot
parent0580901bbb0332547a08f37072a6ff8ca9e7c893commit | diff
[RISCV] Make sure we always call tryShrinkShlLogicImm for ISD:AND during isel.

There was an early out that prevented us from calling this for
(and (sext_inreg (shl X, C1), i32), C2).
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/test/CodeGen/RISCV/narrow-shl-cst.ll diff | blob | history
llvm/test/CodeGen/RISCV/shift-and.ll diff | blob | history
Domain: System / Toolchain;