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(parent: f02e378) | patch
[VP][RISCV] Add vp.bitreverse and RISC-V support.
authorYeting Kuo <yeting.kuo@sifive.com>
Fri, 9 Dec 2022 08:20:04 +0000 (16:20 +0800)
committerYeting Kuo <yeting.kuo@sifive.com>
Mon, 12 Dec 2022 02:58:44 +0000 (10:58 +0800)
commit47b9da72e032f8042d0fdbfef75ecfbb3c6960eb
tree0a1b5ee820156150714d3362cd20131a342d03fbtree | snapshot
parentf02e3782756595c6a2e86353ea155781ef8c5469commit | diff
[VP][RISCV] Add vp.bitreverse and RISC-V support.

The patch also added function expandVPBITREVERSE to expand ISD::VP_BITREVERSE nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139697
12 files changed:
llvm/docs/LangRef.rst diff | blob | history
llvm/include/llvm/CodeGen/TargetLowering.h diff | blob | history
llvm/include/llvm/IR/Intrinsics.td diff | blob | history
llvm/include/llvm/IR/VPIntrinsics.def diff | blob | history
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp diff | blob | history
llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll [new file with mode: 0644] blob
llvm/unittests/IR/VPIntrinsicTest.cpp diff | blob | history
Domain: System / Toolchain;