riscv: Enable KFENCE for riscv64
authorLiu Shixin <liushixin2@huawei.com>
Tue, 15 Jun 2021 03:07:34 +0000 (11:07 +0800)
committerPalmer Dabbelt <palmerdabbelt@google.com>
Thu, 1 Jul 2021 03:55:41 +0000 (20:55 -0700)
commit47513f243b452a5e21180dcf3d6ac1c57e1781a6
treeaa27c8636f678455c2ece08ee1f5caf8d2e8854f
parentf627476e8f1a15495fb363e4a25f495460e8c969
riscv: Enable KFENCE for riscv64

Add architecture specific implementation details for KFENCE and enable
KFENCE for the riscv64 architecture. In particular, this implements the
required interface in <asm/kfence.h>.

KFENCE requires that attributes for pages from its memory pool can
individually be set. Therefore, force the kfence pool to be mapped at
page granularity.

Testing this patch using the testcases in kfence_test.c and all passed.

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Acked-by: Marco Elver <elver@google.com>
Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
arch/riscv/Kconfig
arch/riscv/include/asm/kfence.h [new file with mode: 0644]
arch/riscv/mm/fault.c