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(parent: b2a3974) | patch
usb: dwc3: Update soft-reset wait polling rate
authorThinh Nguyen <Thinh.Nguyen@synopsys.com>
Thu, 8 Aug 2019 23:39:42 +0000 (16:39 -0700)
committerFelipe Balbi <felipe.balbi@linux.intel.com>
Fri, 9 Aug 2019 05:31:38 +0000 (08:31 +0300)
commit4749e0e61241cc121de572520a39dab365b9ea1d
tree9bb5f9f08c454d35eed983c0e2bd2ef70e5f3612tree | snapshot
parentb2a3974253d32374af556541141d7fdad8fe2ce0commit | diff
usb: dwc3: Update soft-reset wait polling rate

Starting from DWC_usb31 version 1.90a and later, the DCTL.CSFRST bit
will not be cleared until after all the internal clocks are synchronized
during soft-reset. This may take a little more than 50ms. Set the
polling rate at 20ms instead.

Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
drivers/usb/dwc3/core.c diff | blob | history
drivers/usb/dwc3/core.h diff | blob | history
Domain: System / Kernel;