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(parent: 2c47b88) | patch
[RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.
authorCraig Topper <craig.topper@sifive.com>
Tue, 13 Jul 2021 06:53:40 +0000 (23:53 -0700)
committerCraig Topper <craig.topper@sifive.com>
Tue, 13 Jul 2021 16:46:21 +0000 (09:46 -0700)
commit46e89708170c40e8cf0305b6de048ca879f43aab
tree57fe10ad0a507da00031a2a05f34c66c01adf4dftree | snapshot
parent2c47b8847ec75c25187e9819abd85cc9e908d742commit | diff
[RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.

Some microarchitectures treat rs1=x1/x5 on jalr as a hint to pop
the return-address stack. We should avoid using x5 on jalr
instructions since we aren't using x5 as an alternate link register.

Differential Revision: https://reviews.llvm.org/D105875
llvm/lib/Target/RISCV/RISCVInstrInfo.td diff | blob | history
llvm/lib/Target/RISCV/RISCVRegisterInfo.td diff | blob | history
llvm/test/CodeGen/RISCV/calls.ll diff | blob | history
llvm/test/CodeGen/RISCV/tail-calls.ll diff | blob | history
Domain: System / Toolchain;