[RISCV][InsertVSETVLI] Split out demanded property for zero/non-zero of VL
authorPhilip Reames <preames@rivosinc.com>
Tue, 3 Jan 2023 22:34:28 +0000 (14:34 -0800)
committerPhilip Reames <listmail@philipreames.com>
Tue, 3 Jan 2023 22:47:13 +0000 (14:47 -0800)
commit46dee4a3a3dfb372a0eaa0b4490c80be2f421f29
treee698b2326f7e9e11b24c6c6a2fe25cab77c6b64d
parent609b789170625277f631139c790c22d527ff1eed
[RISCV][InsertVSETVLI] Split out demanded property for zero/non-zero of VL

The scalar move instructions (vmv.s.x, and fvmv.s.f) depend solely on whether the VL is 0 or non-zero. By tracking the fact we only demand the zeroness and not the whole VL value, we can allow changing VL over a scalar move. This helps to eliminate vsetvli toggles.

Differential Revision: https://reviews.llvm.org/D140157
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll