MSL: Rewrite how IO blocks are emitted in multi-patch mode.
authorHans-Kristian Arntzen <post@arntzen-software.no>
Thu, 8 Apr 2021 09:47:35 +0000 (11:47 +0200)
committerHans-Kristian Arntzen <post@arntzen-software.no>
Mon, 19 Apr 2021 10:10:49 +0000 (12:10 +0200)
commit46c48ee6b5d07d25b2ca54e0eebfc2fd3fd15a30
treeae30c9e59b711496d6b5e3f520bb27941ca7fcd3
parent425e968720cfa1c2ec99e3bb5f4d3bef3c248f3f
MSL: Rewrite how IO blocks are emitted in multi-patch mode.

Firstly, never flatten inputs or outputs in multi-patch mode.
The main scenario where we do need to care is Block IO.
In this case, we should only flatten the top-level member, and after
that we use access chains as normal.

Using structs in Input storage class is now possible as well. We don't
need to consider per-location fixups at all here. In Vulkan, IO structs
must match exactly. Only plain vectors can have smaller vector sizes as
a special case.
16 files changed:
reference/opt/shaders-msl/desktop-only/tesc/struct-copy.desktop.sso.multi-patch.tesc
reference/opt/shaders-msl/masking/write-outputs.mask-location-0.for-tess.vert
reference/opt/shaders-msl/masking/write-outputs.mask-location-1.for-tess.vert
reference/opt/shaders-msl/masking/write-outputs.mask-point-size.for-tess.vert
reference/opt/shaders-msl/tesc/complex-patch-out-types.tesc [new file with mode: 0644]
reference/opt/shaders-msl/tesc/load-control-point-array-of-struct.multi-patch.tesc
reference/shaders-msl-no-opt/asm/tesc/tess-fixed-input-array-builtin-array.invalid.multi-patch.asm.tesc
reference/shaders-msl/desktop-only/tesc/struct-copy.desktop.sso.multi-patch.tesc
reference/shaders-msl/masking/write-outputs.mask-location-0.for-tess.vert
reference/shaders-msl/masking/write-outputs.mask-location-1.for-tess.vert
reference/shaders-msl/masking/write-outputs.mask-point-size.for-tess.vert
reference/shaders-msl/tesc/complex-patch-out-types.tesc [new file with mode: 0644]
reference/shaders-msl/tesc/load-control-point-array-of-struct.multi-patch.tesc
shaders-msl/tesc/complex-patch-out-types.tesc [new file with mode: 0644]
spirv_msl.cpp
spirv_msl.hpp