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(parent: 6cc859c) | patch
clk: renesas: rzg2l: Add DSI divider clk support
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 30 Apr 2022 11:41:50 +0000 (12:41 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 5 May 2022 10:10:21 +0000 (12:10 +0200)
commit46bb3e15e8c7e6c045f619e91b380ff090669b83
treeff0e0959eea284a7b0377111c9d9ee417eab0e49tree | snapshot
parent6cc859cae9aa8c42e8347e2806232bdffeb1b33dcommit | diff
clk: renesas: rzg2l: Add DSI divider clk support

M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB)

This patch add support for DSI divider clk by combining
DSIDIVA and DSIDIVB.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/rzg2l-cpg.c diff | blob | history
drivers/clk/renesas/rzg2l-cpg.h diff | blob | history
Domain: System / Kernel;