[SVE][CodeGen] Fix bug in DAGCombiner::reduceBuildVecToShuffle
authorDavid Sherwood <david.sherwood@arm.com>
Thu, 25 Jun 2020 13:46:16 +0000 (14:46 +0100)
committerDavid Sherwood <david.sherwood@arm.com>
Tue, 30 Jun 2020 06:28:15 +0000 (07:28 +0100)
commit46a7f4d6f4bf2cc23a410e771adb587c5968047d
tree4c7bcb6a5e67bf108b2a7be5396d4682b0e2d609
parent6b9a706200cbb27e5e863cfd41fb3684ee616e23
[SVE][CodeGen] Fix bug in DAGCombiner::reduceBuildVecToShuffle

When trying to reduce a BUILD_VECTOR to a SHUFFLE_VECTOR it's
important that we carefully check the vector types that led to
that BUILD_VECTOR. In the test I have attached to this commit
there is a case where the results of two SVE faddv instructions
are being stored to consecutive memory locations. With my fix,
as part of merging those stores we discover that each BUILD_VECTOR
element came from an extract of a SVE vector element and
therefore bail out.

Differential Revision: https://reviews.llvm.org/D82564
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/AArch64/sve-merging-stores.ll [new file with mode: 0644]