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(parent: 23f69df) | patch
i965: Port gen6+ 3DSTATE_WM to genxml.
authorRafael Antognolli <rafael.antognolli@intel.com>
Tue, 21 Mar 2017 21:55:50 +0000 (14:55 -0700)
committerKenneth Graunke <kenneth@whitecape.org>
Thu, 4 May 2017 01:57:51 +0000 (18:57 -0700)
commit46934d959418d297c576cc54631dd3c2aa89f822
tree0e75680cbae550a93500760949482dca0aae9028tree | snapshot
parent23f69dfc0f5eabc04141e9a2793cf871f38d6432commit | diff
i965: Port gen6+ 3DSTATE_WM to genxml.

Emit 3DSTATE_WM on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use render_bo helper to setup brw_address (Kristian)
   - Remove TODO and use BRW_PSCDEPTH_OFF.
v3:
   - A couple of style fixes (Ken)
   - Enable RASTRULE_UPPER_RIGHT on gen6+ instead of gen8+ (Ken)

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/Makefile.sources diff | blob | history
src/mesa/drivers/dri/i965/brw_state.h diff | blob | history
src/mesa/drivers/dri/i965/gen6_wm_state.c diff | blob | history
src/mesa/drivers/dri/i965/gen7_wm_state.c [deleted file] blob | history
src/mesa/drivers/dri/i965/gen8_ps_state.c diff | blob | history
src/mesa/drivers/dri/i965/genX_state_upload.c diff | blob | history
Domain: Graphics System / GL;