powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
authorAneesh Bansal <aneesh.bansal@freescale.com>
Tue, 16 Jun 2015 05:06:00 +0000 (10:36 +0530)
committerYork Sun <yorksun@freescale.com>
Fri, 31 Jul 2015 15:50:18 +0000 (08:50 -0700)
commit467a40dfe35f48d830f01a72617207d03ca85b4d
tree611ccbd0ca161a8abd72b1481e7ac05547969887
parent7842950f7c05aa9d901308d149ad3d67237bb315
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.

In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Makefile
arch/powerpc/cpu/mpc85xx/start.S
arch/powerpc/include/asm/fsl_secure_boot.h
board/freescale/common/p_corenet/tlb.c
board/freescale/corenet_ds/MAINTAINERS
configs/P3041DS_NAND_SECURE_BOOT_defconfig [new file with mode: 0644]
include/configs/corenet_ds.h