MAINTAINERS: Add entry for Renesas RISC-V
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Fri, 28 Oct 2022 16:59:20 +0000 (17:59 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 10 Nov 2022 15:36:34 +0000 (16:36 +0100)
commit461e1857d6bf15cf5df103383e255f3425ac0038
tree873bc62a02a53cd4405bb6aaa3f7008ed9cfa798
parent4adb690aa1b41c1e52af579574d1d6aa58da1187
MAINTAINERS: Add entry for Renesas RISC-V

Add RISC-V architecture as part of ARM/Renesas architecture, as they have
the same maintainers, use the same development collaboration
infrastructure, and share many files.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221028165921.94487-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
MAINTAINERS