AMDGPU: Created a subclass for the return address operand in the tail call return...
authorChangpeng Fang <changpeng.fang@amd.com>
Tue, 4 Apr 2023 17:56:58 +0000 (10:56 -0700)
committerChangpeng Fang <changpeng.fang@amd.com>
Tue, 4 Apr 2023 17:56:58 +0000 (10:56 -0700)
commit461a559bc9bd755436ba8f12f8b74757e03f9b9f
treeff3ca607fcffcc122efdf51037f9cab9dc0acf22
parent96c23c9c996333e2809251b9559498c40ddbc6a5
AMDGPU: Created a subclass for the return address operand in the tail call return instruction

Summary:
  This is to avoid using the callee saved registers for the return address of the tail call return instruction.

Reviewers:
  arsenm, cdevadas

Differential Revision:
  https://reviews.llvm.org/D147096
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll