[PORT FROM R2]mid_pmu: increase delay while looping for c6 write access bit check

[PORT FROM R2]mid_pmu: increase delay while looping for c6 write access bit check

BZ: 17718

Based on Continente, Christophe <christophe.continente@intel.com> initial
patch #31029, that puts infinite delay while checking c6 write access bit, the
black screen issue while charging is not seen even after 200+ hours of
running, while without the patch #31029 it is observed within 15+ hours

On this observation I'm putting this delay of upto 500usecs in
1usec granularity, while looping for c6 write access bit set,
also we wait for pm_msic bit to be set indicating that the PM_CMD processing
has started in SCU.

Based on Onkalo Samu's suggestion added c6offload bit clear in
pmu_sc_irq for s0ix command completion interrupts.

The reason for clearing c6 offload bit in pm_sc_irq is for the following:

There could be a previous s0i3 command submitted and c6offload bit might
have been set and also c6 offload write access bit is also set by SCU
but because of need_reschd() set we may skip mwait(C6), the next time
a normal C6 happens *after* pm_scu_irq P-unit may errorneously do c6
offload.

Change-Id: I0ebab3fdb97763aacee62007eb95f0f31b6fb9e2
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
Reviewed-on: http://android.intel.com:8080/32177
Reviewed-by: Hogander, Jouni <jouni.hogander@intel.com>
Tested-by: Martin, LoicX <loicx.martin@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>