drm/i915/psr: Fix BDW PSR AUX CH data register offsets
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 9 Jun 2023 14:13:53 +0000 (17:13 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 16 Jun 2023 14:54:47 +0000 (17:54 +0300)
commit460dc4ba1442b3e5e543328d11db2702b98d3d7c
tree41ea1b3c6757c364e56a65662abae7f97a60ad3e
parent5197c49d20e39ee5dd60df2272ae6fe6cf7ebfe9
drm/i915/psr: Fix BDW PSR AUX CH data register offsets

The multiplication got replaced by an addition in some cleanup.
This means we never write the correct data to some of the BDW
PSR data registers and thus we fail to actually wake up the
panel from PSR.

Fixes: 4ab4fa103217 ("drm/i915/psr: Make PSR registers relative to transcoders")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-3-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
drivers/gpu/drm/i915/display/intel_psr_regs.h