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[AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering::hasAndNot
authorDavid Sherwood <david.sherwood@arm.com>
Tue, 16 Nov 2021 14:19:18 +0000 (14:19 +0000)
committerDavid Sherwood <david.sherwood@arm.com>
Tue, 16 Nov 2021 16:25:16 +0000 (16:25 +0000)
commit460745902275c341889bde9daeb41287359e59e3
treee54681f1756144ddf0c070e0814480e52af25ab0tree | snapshot
parent35f798d05d5138613e1392ec1630eec93b0caff9commit | diff
[AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering::hasAndNot

For now I've just changed the code to only return true from
AArch64ISelLowering::hasAndNot if the vector is fixed-length.
Once we have the right patterns or DAG combines to use bic/bif
we can also enable this for SVE.

Test added here:

  CodeGen/AArch64/vselect-constants.ll

Differential Revision: https://reviews.llvm.org/D113994
llvm/lib/Target/AArch64/AArch64ISelLowering.h diff | blob | history
llvm/test/CodeGen/AArch64/vselect-constants.ll diff | blob | history
Domain: System / Toolchain;