clk: Add support for fundamental zynq clks
authorJosh Cartwright <josh.cartwright@ni.com>
Tue, 13 Nov 2012 23:26:48 +0000 (17:26 -0600)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 14 Nov 2012 15:07:55 +0000 (16:07 +0100)
commit45aa2c27ada4829bc91bd80455bc67059ac06bc5
tree988c0d412a6a59414b80eeb02813923032841476
parente06f1a9ed7ebff170ba05d2606d079fb36c6a52d
clk: Add support for fundamental zynq clks

Provide simplified models for the necessary clocks on the zynq-7000
platform.  Currently, the PLLs, the CPU clock network, and the basic
peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled.

OF bindings are also provided and documented.

Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Documentation/devicetree/bindings/clock/zynq-7000.txt [new file with mode: 0644]
drivers/clk/clk-zynq.c [new file with mode: 0644]
include/linux/clk/zynq.h [new file with mode: 0644]