IVGCVSW-2102: Fix Pooling2D CpuRef indexing bug
authorJames Conroy <james.conroy@arm.com>
Wed, 31 Oct 2018 11:47:53 +0000 (11:47 +0000)
committerJames Conroy <james.conroy@arm.com>
Wed, 31 Oct 2018 12:06:53 +0000 (12:06 +0000)
commit45a9b775bf63283320315d90e4e9a6c641df6e20
treee1f0d33d98410255a6804ea9cccf16805fc6080f
parentd84216a013445e86183e39c8b5b904836c71a95b
IVGCVSW-2102: Fix Pooling2D CpuRef indexing bug

* Fixes bug when calcuating indexes for NHWC in
  Pooling2D CpuRef implementation, it now uses
  TensorBufferArrayView.
* Adds 2-Channel unit tests for Pooling2d on CpuRef,
  Cl and Neon. The single channel tests were not
  properly exercising Pooling2d using NHWC data layout.
* Refactors Pooling2D NHWC tests so that the input and
  output data are permuted to NHWC when necessary,
  instead of hard coding the data in NHWC format.

Change-Id: I5b9d41ed425ff283ea8c8ef6b1266ae0bc80f43b
src/armnn/test/TensorHelpers.hpp
src/backends/cl/test/ClLayerTests.cpp
src/backends/neon/test/NeonLayerTests.cpp
src/backends/reference/test/RefLayerTests.cpp
src/backends/reference/workloads/Pooling2d.cpp
src/backends/test/Conv2dTestImpl.hpp
src/backends/test/LayerTests.cpp
src/backends/test/LayerTests.hpp
src/backends/test/Pooling2dTestImpl.hpp