[InstCombine] Only propagate known leading zeros from udiv input to output.
authorBenjamin Kramer <benny.kra@googlemail.com>
Thu, 10 May 2018 11:45:18 +0000 (11:45 +0000)
committerBenjamin Kramer <benny.kra@googlemail.com>
Thu, 10 May 2018 11:45:18 +0000 (11:45 +0000)
commit456f473ea8f2ca7b85773ba09140c5862f9c3ad7
treeaeeb86c7e6f027624513417d4c75b7d8a0a81858
parent70f4eaf699d2562adc16b9d6346e788cd318336d
[InstCombine] Only propagate known leading zeros from udiv input to output.

Put in a conservatively correct estimate for now. Avoids miscompiling
clang in FDO mode. This is really tricky to trigger in reality as
basically all interesting cases will be folded away by computeKnownBits
earlier, I was unable to find a reasonably small test case.

llvm-svn: 331975
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp