[RISCV] Explicitly select second operand of branch condition to X0.
authorCraig Topper <craig.topper@sifive.com>
Mon, 1 Aug 2022 18:16:48 +0000 (11:16 -0700)
committerCraig Topper <craig.topper@sifive.com>
Mon, 1 Aug 2022 18:16:48 +0000 (11:16 -0700)
commit450edb0b376687dc15c62c1c050e2222de7a2902
tree11118929d7ac38a2fec297a8e3c68d55b2127b0f
parent3879d3edef89879112080f57f0a9edf15d8d92a4
[RISCV] Explicitly select second operand of branch condition to X0.

At least based on the lit tests, the coalescer sometimes fails to
propagate the copy from X0 into the branch instruction. This patch
does it manually during isel. The majority of the changes are from
the select patterns.

Some of the changes are just register allocation changes. Only
the Select change affects the whether a b*z instruction is generated
in the tests. I changed the branch pattern for consistency.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D130809
14 files changed:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
llvm/test/CodeGen/RISCV/double-convert.ll
llvm/test/CodeGen/RISCV/float-convert.ll
llvm/test/CodeGen/RISCV/fpclamptosat.ll
llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
llvm/test/CodeGen/RISCV/half-convert.ll
llvm/test/CodeGen/RISCV/rv32zbb-zbp-zbkb.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
llvm/test/CodeGen/RISCV/shifts.ll