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(parent: 631330f) | patch
MIPS: Hibernation: Remove SMP TLB and cacheflushing code.
authorRalf Baechle <ralf@linux-mips.org>
Fri, 19 Jun 2009 14:01:44 +0000 (15:01 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 24 Jun 2009 17:34:39 +0000 (18:34 +0100)
commit44eeab67416711db9b84610ef18c99a60415dff8
treee9beb9000be5cd9c17bbb7bc05cd3db1c4cb3f09tree | snapshot
parent631330f5847b3f8a7ea67d689e9f7c56833ccaa6commit | diff
MIPS: Hibernation: Remove SMP TLB and cacheflushing code.

We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled.  A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled.  A local
flush is not needed either because we didn't change any mappings.  So
just delete the code.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/power/hibernate.S diff | blob | history
Domain: System / Kernel;