[fastregalloc] Enhance the heuristics for liveout in self loop.
authorLuo, Yuanke <yuanke.luo@intel.com>
Tue, 21 Jun 2022 00:10:16 +0000 (08:10 +0800)
committerLuo, Yuanke <yuanke.luo@intel.com>
Tue, 21 Jun 2022 01:18:49 +0000 (09:18 +0800)
commit44e8a205f4cf747b920726428ee9e35c2ac3d706
tree0fbfb17694346d6d6da40b8997dd4333ced1f00b
parentd883a02a7c2bb89000d0685749f062c9206ac40c
[fastregalloc] Enhance the heuristics for liveout in self loop.

For below case, virtual register is defined twice in the self loop. We
don't need to spill %0 after the third instruction `%0 = def (tied %0)`,
because it is defined in the second instruction `%0 = def`.

1 bb.1
2 %0 = def
3 %0 = def (tied %0)
4 ...
5 jmp bb.1

Reviewed By: MatzeB

Differential Revision: https://reviews.llvm.org/D125079
llvm/lib/CodeGen/RegAllocFast.cpp
llvm/test/CodeGen/AArch64/atomicrmw-O0.ll
llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
llvm/test/CodeGen/X86/atomic32.ll
llvm/test/CodeGen/X86/atomic64.ll
llvm/test/CodeGen/X86/atomic6432.ll
llvm/test/CodeGen/X86/fastregalloc-selfloop.mir
llvm/test/CodeGen/X86/swifterror.ll
llvm/test/DebugInfo/X86/fission-ranges.ll